1. Field of the Invention
This invention relates to lithographic processing of microelectronics products and, in particular, to a method and system for simulating an optical critical dimension metrology system used to evaluate the effects of dose and focus during lithographic processing
2. Description of Related Art
Lithographic processing to produce microelectronic circuits on semiconductor wafers requires, among other things, optimization of exposure dose and focus of the energy source used to expose the mast films. An optical critical dimension (OCD) metrology system evaluates dose and/or focus response in a lithographic imaging system by measuring the changes in a printed target, for example, the length of printed lines, in a focus/dose matrix.
Conventional lithography simulators are designed to model the imaging of manhattan-type mask patterns onto the wafer. It has been found that conventional lithography simulators are inadequate in modeling an OCD metrology system because of their inability to treat the complicated shapes represented by the contours of the printed lines. Further, conventional simulation methods represent targets and their printed images as thresholded bitmaps. This quantization hinders the process of design refinement, because it becomes harder to achieve convergence during optimization of the shapes when the model response exhibits discontinuities that are not present in the physical system. While more sophisticated simulators attempt to deal with more complex shapes such as polygons, their treatment of the polygons involves breaking them down into simpler shapes such as rectangles and triangles, which is not fully satisfactory. Additionally, it is believed that the computational cost of deploying a solution tied to these simulators would be very high.
Accordingly, there is a need for simulation of an OCD metrology system in order to explain certain unexpected behaviors, as well as assist in designing targets that best monitor dose/focus response of the features that arise in the various levels of a chip.